View SL2309ZI-1HT_3765817.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev 1.3, july 31, 2007 page 1 of 12 400 west cesar chavez, austin, t x 78701 1+(512) 416 - 8500 1+(512) 416 - 9669 www.silabs.com sl2309 ? key features ? 10 to 140 mhz operating frequency range ? low output clock jitter: ? 140 ps - max cycle -to - cycle jitter ? low output -to - output skew: 15 0 ps - max ? low product - to - product skew: 400 ps - max ? 3.3 v power supply range ? low power dissipation: ? 26 m a- max at 66 mhz ? 44 ma ? max at 133 mhz ? one input drives 9 outputs organized as 4+4+1 ? select mode to bypass pll or tri - state outputs ? spreadthru ? pll that allows use of sscg ? standard and high - drive options ? available in 16 - pin soic and tssop packages ? available in commercial and industrial grades applications ? printers and mfps ? digital copiers ? pcs and work stations ? dtv ? routers, switchers and servers ? digital embeded systems description the sl23 09 is a low skew, low jitter and low power zero delay buffer (zdb) designed to produce up to nine (9) clock outputs from one (1) reference input clock, for high speed clock distribution applications. the product has an on - chip pll which locks to the input clock at clkin and receives its feedback internally from the clkout pin. the sl23 09 has two (2) clock driver banks each with four (4) clock outputs. these outputs are controlled by two (2) select input pins s1 a nd s2. when only four (4) outputs are needed, four (4) bank - b output clock buffers can be tri - stated to reduce power dissipation and jitter. the select inputs can also be used to tri - state both banks a and b or drive them directly from the input bypassing the pll and making the product behave like a non - zero delay fanout buffer (nzdb). the high - drive (- 1h) versio n operates up to 140 mhz and low drive (-1) version operates up to 100mhz at 3.3v . benefits ? up to nine (9) distribution of input clock ? standard and high -d rive levels to control impedance level, frequency range and emi ? low power dissipation, jitter and skew ? low cost block diagram low power and low jitter pll mux input selection decoding logic vdd gnd 2 2 s2 s1 clkin clkout clka1 clka2 clka3 clka4 clkb1 clkb2 clkb3 clkb4 low jitter and skew 10 to 140 mhz zero delay buffer (zdb)
rev 1.3, july 31, 2007 page 2 of 12 sl2309 pin configuration clka1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 clkout clka4 clka3 vdd gnd clkb4 clkb3 s1 clkin clka2 vdd gnd clkb1 clkb2 s2 pin description 16 - pin soic and tssop pin number pin name pin type pin description 1 clkin input reference frequency clock input. weak pull - down (2 50k ). 2 clka1 output buffered clock ou tput, bank a. weak pull - down (2 50k). 3 clka2 output buffered clock ou tput, bank a. weak pull - down (2 50k). 4 vdd power 3.3v power supply. 5 gnd power power ground. 6 clkb1 output buffered clock output , bank b . weak pull - down (2 50k). 7 clkb2 output buffered clock ou tput, bank b. weak pull - down (2 50k). 8 s2 input select input , select pin s2. weak pull - up (2 50k). 9 s1 input select input , select pin s1. weak pull - up (2 50k). 10 clkb3 output buffered clo ck ou tput, bank b. weak pull - down (2 50k). 11 clkb4 output buffered clock o utput, bank b. weak pull - down (2 50k). 12 gnd power power ground. 13 vdd power 3.3v power supply. 14 clka3 output buffered clock output, bank a. weak pull - down (2 50k). 15 clka4 output buffered clock ou tput, bank a. weak pull - down (2 50k). 16 clkout output buffered clock output, pll internal feedback out put. weak pull - down ( 2 50k).
rev 1.3, july 31, 2007 page 3 of 12 sl2309 general description the sl23 09 is a low skew, low jitter zero delay buffer with ver y low operating current. the product includes an on - chip high performance pll that locks into the input reference clock and produces nine (9) output clock drivers tracking the input reference clock for systems requiring clock distribution. i n addition to c lkout that is used for internal pll feedback, there are two (2) banks with four (4) outputs in each bank, bringing the number of total available output clocks to nine (9). input and o utput frequency range the input and output frequency range is the sam e . but, it depends on the drive and output load ( cl ) levels as given in the below table 1. drive cl(pf) min(mhz) max(mhz) high 15 10 140 high 30 10 100 low 15 10 100 low 30 10 66 table 1. input/output frequency range if t he input clock is dc (gnd t o vdd) or floating, this is detected by an input frequency detection circuitry and all nine (9) clock outputs are forced to hi -z. the pll is shutdown to save power. in this shutdown state , the product draws less than 12 a - max supply current. in pll by - pass mode (s2=1 and s1=0), the detection circuit is disabled and input frequency range is 1 0 to 100mhz for standard ( - 1) drive and 10 to 140 mhz for high (- 1h) drive. spreadthru ? feature if a spread spectrum clock (ssc) we re to be us ed as an input clock, the sl23 09 is designed to pass the modulated spread spectrum clock (ssc) signal from its reference input to the output clocks. the same spread characteristics at the input are passed through the pll and drivers without any degradation in spread percent (%), spread profile and modulation frequency select input control (s2, s1) the sl23 09 provides two (2) input select control pins called s1 (pin - 9) and s2 (pin -8) . this f eature enables users to select various states o f output clock banks - a and bank - b, output source and pll shutdown features as shown in the table 2. the s1 (pin -9) and s2 (pin - 8) inputs include 250 k weak pull - up resistors to vd d. pll bypass mode if the s1 and s2 pins are logic low(0) and high(1) respective ly, the on - chip pll is shutdown and bypassed, and all the nine output clocks ; bank a, bank b and clkout clocks are driven by directly from the reference input cloc k. in this operation mode sl23 09 works like a non- zdb fanout buffer . in this operation mode the input power - down detection circuit is disabled and outputs follow the input clock from dc to rated frequencies based on drive levels and load specifications. high and low - drive product options the sl23 09 is offered wit h high drive ? - 1h? and standar d drive ? - 1? options. these drive options enable the users to control load levels, frequency range and emi. refer to the switching electrical tables for the details. skew and zero delay all outputs should drive the similar load to achieve the output - t o - output skew and input -to - outpu t specifications given in the switching el ectrical tables. however, zero d elay between input and outputs can be adj usted by changing the loading at clkout relative to the banks a and b clocks since clkout is the feedback to the pll. power supply range (vdd) the sl23 0 9 is designed to operate at vdd=3.3v (+/ - 10%) . an internal on - chip vol tage regulator is used to provide pll constant power supply of 1.8v, leading to a consistent and stable pll electrical performance in terms of skew, jitter and power dissipation. sl23ep09 refer to sl23ep09 for extended frequency operation from 10 to 220mhz and 2.5v to 3.3v power supply operation range.
rev 1.3, july 31, 2007 page 4 of 12 sl2309 0 5 10 15 20 25 30 -30 -25 -20 -5 -10 -15 1500 1000 500 -500 -1500 -1000 0 output load difference: fbk load ? clka or clkb load (pf) clkin input to clka or clkb delay (ps ) figure 1. clkin input to clk a and b delay (in terms of load differen ce between clkout and clk a and b) s2 s1 clock a1 - a4 clock b1 - 4 clkout output source pll status 0 0 tri - state tri - state driven pll o n 0 1 driven tri - state driven pll on 1 0 driven driven driven reference off 1 1 driven driven driven pll on table 2. select input decoding
rev 1.3, july 31, 2007 page 5 of 12 sl2309 absolute maximum ratings operating conditions: unless otherwise stated vdd=3.3v+/ - 10% and both c and i grades description condition min max unit supply voltage, vdd ? 0.5 4.6 v all inputs and outputs ? 0.5 vdd+0.5 v ambient operating temperature in operation, c - grade 0 70 c ambient operating temperature in operation, i - grade ? 40 85 c storage temperature no power is applied ? 65 150 c junction temperature in operation, power is applied ? 125 c soldering temperature ? 260 c esd rating (human body model) jedec22 - a114d - 4,000 4,000 v esd rating (charge device model) jedec22 - c101c - 1,500 1,500 v esd rating (machine model) jedec22 - a115d -250 250 v latch -up 125c -200 200 ma symbol description conditi on min max unit vdd 3.3v supply voltage 3.3v+/ - 10% 3.0 3.6 v ta operating temperature(ambient) commercial 0 70 c industrial ? 40 85 c cload load capacitance 10 to 140 mhz, - 1h high drive all active pll modes ? 15 pf 10 to 100 mhz, -1 h high drive all active pll modes ? 30 pf 10 to 100mhz, - 1 standard drive all active pll modes ? 15 pf 10 to 66mhz, - 1 standard drive all active pll modes ? 30 pf cin input capacitance s1, s2 and clkin pins ? 7 pf tpu power - up time power -up t ime for all vdds to reach minimum vdd voltage (vdd=3.0v). 0.05 100 ms clbw closed - loop bandwidth 3.3v, (typical) 1.2 mhz zout output impedance 3.3v, (typical), - 1h high drive 22 ? 3.3v, (typical), - 1 standard drive 32 ?
rev 1.3, july 31, 2007 page 6 of 12 sl2309 dc electr ical specifica tions: unless otherwise stated vdd=3.3v+/ - 10% and both c and i grades symbol description condition min max unit vdd supply voltage 3.0 3.6 v vil input low voltage clkin, s2 and s1 pins ? 0.8 v vih input high voltage clkin, s2 and s1 pins 2.0 v dd +0.3 v iil input low current clkin, s2 and s1 pins, 0 < vin < 0.8v ? 25 a iih input high current clkin, s2 and s1 pins, vin = vdd ? 50 a vol output low voltage (all outputs) iol = 8 ma (standard drive) ? 0.4 v iol = 12 ma ( high drive) ? 0.4 v voh output high voltage (all outputs) ioh = ? 8 ma (standard drive) 2.4 ? v ioh = ? 12 ma (high drive) 2.4 ? v iddpd power down supply current clkin =0 to vdd or floating (input will be pulled - down by 2 50k weak pull - down on - ch ip resistor) c - grade ? 12 a i - grade ? 25 a idd 1 power supply current all outputs cl=0, 33 mhz clkin s2=s1=1 (high) ? 14 ma idd2 power supply current all outputs cl =0, 66 mhz clkin s2=s1=1 (high) ? 2 6 ma idd 3 power supply current all outputs cl=0, 100 mhz clkin s2=s1=1 (high) ? 36 ma idd 4 power supply current all outputs cl=0, 133 mhz clkin s2=s1=1 (high) ? 44 ma rpu/d pull - up and pull - down resistors pins - 1/2/3/6/7/8/9/10/11/14/15/16 250k - typ 175 325 k
rev 1.3, july 31, 2007 page 7 of 12 sl2309 switching s pecifications: unless otherwise stated vdd=3.3v+/ - 10% and both c and i grades notes: 1. for the given maximum loading conditions. see cl in operating conditions table. 2. parameter is guaranteed by design and characterization. not 100% tested in production. symbol description condition min typ max unit fmax 1 maximum frequency (input=output ) [1] all active pll modes high d rive (- 1h). all outputs cl=1 5 pf 10 ? 140 mhz high d rive ( - 1h), all outputs cl=30pf 10 ? 100 mhz standard d rive, ( - 1), all outputs cl=15pf 10 ? 100 mhz standard d rive, ( - 1), all outputs cl=30pf 10 ? 66 mhz fmax2 maximum frequency (input=output ) [1] pll bypass mode (s2=1 and s1=0) hig h drive ( - 1h). all outputs cl=15pf 0 ? 140 mhz high drive ( - 1h), all outputs cl=30pf 0 ? 100 mhz standar d drive, ( - 1), all outputs cl=15pf 0 ? 100 mhz standa rd drive, ( - 1), all outputs cl=3 0pf 0 ? 66 mhz indc input duty cycle measured at 1.4v, fout=66mhz, cl=15pf 30 50 70 % outdc 1 output duty cycle measured at 1.4v, fout=66mhz, cl=15pf [2] 40 50 60 % outdc2 output duty cycle measured at 1.4v, fout=66mhz, cl=15pf [2] 40 50 60 % tr/f rise, fall time (3.3v) (measured at: 0.8 to 2.0v) [2] high drive ( - 1h), cl=15pf ? ? 1.5 ns high drive ( - 1h), cl=30pf ? ? 1.8 ns standard drive ( - 1), cl=15pf ? ? 2.2 ns standard drive ( - 1), cl=30pf ? ? 2.5 ns t1 output -to - output skew (measure d at vdd/2) [2] all outputs cl=0 or equally loaded, - 1 or - 1h drives ? 70 150 ps t2 product -to - product skew (measured at vdd/2) [2] all outputs cl=0 or equally loaded, - 1 or - 1h drives ? 180 400 ps t3 delay time, clkin rising edge to clkout rising edge (measured at vdd/2) [2 ] pll bypass mode only when s2=1 and s1=0 1.5 5 8.7 ns pll enabled all active pll modes ? 220 ? 220 ps tplock pll lock time time from 90% of vdd to valid clocks on all the output clocks [2] ? ? 1.0 ms ccj cycle -to - cycle jitter fin=fout=66 mhz, rev 1.3, july 31, 2007 page 8 of 12 sl2309 external components & design considerations typical application schematic sl2309 cl cl cl 0.1f 0.1f clkin clkout clka1 clkb4 gnd gnd s1 s2 vdd vdd 1 4 13 9 8 5 12 11 2 16 vdd comments and recommendations decoupling capacitor: $ghfrxsolqjfdsdflwruri)pxvwehxvhgehwzhhq9''dqg966slqv3odfhwkhfdsdflwru s on the component side of the pcb as close to the vdd pin s as possible. the pcb trace to the vdd pin and to the gnd via should be kept as short as possible. do not use vias between the decoupling capacitor and the vdd pin. series termination resistor : a series termination resistor is recommended if the distance between the output clocks and the load is over 1 ? inc h. the nominal impedance of the clock outputs is given on the page 4. place the series termination resistors as close to the clock outputs as possible. zero delay and skew control: all outputs and clkin pins should be loaded with the same load to achieve ? zero delay? between the clkin and the outputs. the clkout pin is connected to clkin internally on - chip for feedback to pll, and se es an additional 2 pf load with respect to bank a and b clocks. for applications requiring zero input/output delay, the load a t the all output pins including the clkout pin must be the same. if any delay adjustment is required, the capacitance at the clkout pin could be increased or decreased to increase or decrease the delay between bank a and b clocks and clkin. for minimum pi n -to - pin skew, the external load at all the bank a and b clocks must be the same.
rev 1.3, july 31, 2007 page 9 of 12 sl2309 switching waveforms output vdd/2 vdd/2 output t 1 input vdd/2 vdd/2 clkout t 2 figure 3. input -to - output skew t 3 any output part 1 or 2 vdd/2 vdd/2 any output part 2 or 1 figure 2 . output to output skew figure 4 . part - to - part skew
rev 1.3, july 31, 2007 page 10 of 12 sl2309 package drawing and dimensions 16-lead tssop (4.4-mm) 0.190(0.007) 0.300(0.012) 0.090(0.003) 0.200(0.008) 8 9 6.250(0.246) 6.500(0.256) 4.300(0.169) 4.500(0.177) 4.900(0.193) 5.100(0.200) 0.850(0.033) 0.950(0.037) 0.050(0.002) 0.150(0.006) 1.100(0.043) max 0.076(0.003) 0 to 8 0.500(0.020) 0.700(0.027) 0.650(0.025) bsc gauge plane dimensions are in milimeters(inches). top line : (min) and bottom line : (max) pin-1 id seating plane 1 16 0.650(0.025) bsc thermal characteristics parameter symbol condition min typ max unit thermal resistance junction to ambient ja still air - 80 - c/w ja 1m/s air flow - 70 - c/w ja 3m/s air flow - 68 - c/w thermal resistance junction to case jc independent of air flow - 36 - c/w
rev 1.3, july 31, 2007 page 11 of 12 sl2309 package drawing and dimensions (cont.) 8 0.150( 3.810) 0.157(3.987 0.230( 5.842) 0.244(6.197 ) 0.386(9.804 ) 0.393(9.982) 0.050(1.270) bsc 0.004(0.102 ) seating plane 0.004(0.102) 0.0098(0.249) 0.061(1.549 ) 0.068(1.727) 0 to 8 0.010(0.2540 ) 0.016(0.406) x 45 0.016(0.406 ) 0.035(0.889) 0.0075(0.190 ) 0.0098(0.249 ) pin-1 id dimensions are in inches(milimeters). top line : (min) and bottom line : (max) 16-lead soic (150-mil) 1 9 16 0.0138(0.350) 0.0192(0.487 ) therma l characteristics parameter symbol condition min typ max unit thermal resistance junction to ambient ja still air - 120 - c/w ja 1m/s air flow - 115 - c/w ja 3m/s air flow - 105 - c/w thermal resistance junction to case jc independent of air flow - 60 - c/w
rev 1.3, july 31, 2007 page 12 of 12 sl2309 ordering information [3] ordering number marking shipping package package temperature sl2309zc - 1 sl2309zc - 1 tube 16 - pin tssop 0 to 70c sl2309zc - 1t sl2309zc - 1 tape and reel 16 - pin tssop 0 to 70c sl2309zc -1h sl2309zc -1h tube 16-p in tssop 0 to 70c sl2309zc - 1ht sl2309zc - 1h tape and reel 16 - pin tssop 0 to 70c sl2309zi - 1 sl2309zi - 1 tube 16 - pin tssop - 40 to 85c sl2309zi - 1t sl2309zi - 1 tape and reel 16 - pin tssop - 40 to 85c sl2309zi - 1h sl2309zi - 1h tube 16 - pin tssop - 40 to 85c sl 2309zi - 1ht sl2309zi - 1h tape and reel 16 - pin tssop - 40 to 85c sl2309sc - 1 sl2309sc - 1 tube 16 - pin soic 0 to 70c sl2309sc - 1t sl2309sc - 1 tape and reel 16 - pin soic 0 to 70c sl2309sc - 1h sl2309sc - 1h tube 16 - pin soic 0 to 70c sl2309sc - 1ht sl2309sc - 1h tape a nd reel 16 - pin soic 0 to 70c sl2309si - 1 sl2309si - 1 tube 16 - pin soic - 40 to 85c sl2309si - 1t sl2309si - 1 tape and reel 16 - pin soic - 40 to 85c sl2309si - 1h sl2309si - 1h tube 16 - pin soic - 40 to 85c sl2309si - 1ht sl2309si - 1h tape and reel 16 - pin soic - 40 to 85c notes: 3. the sl23 09 products are rohs compliant. the information in this document is believed to be accurate in all respects at the time of publication but is subject to chan ge without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. additionally, silicon laboratories assumes no responsibility for the functioning of u ndescribed features or parameters. silic on laboratories reserves the right to make changes without further notice. silicon laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories assume any li ability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation consequential or incidental damages. silicon laboratories products are not designed, intended, or author ized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratori es product could create a situation where personal injury or death may occur. should buyer purchase or use silicon laboratories products for any such unintended or unauthorized application, buyer shall indemnify and hold silicon laboratories harmless against all claims and d amages.

▲Up To Search▲

Price & Availability of SL2309ZI-1HT

	To Download SL2309ZI-1HT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .